Arc 10 · Staff AI Engineer
Inference, Training, and AI Infrastructure
Connect model execution to hardware reality: memory movement, precision, batching, parallelism, schedulers, storage, and failure recovery.
Exit capability: Capacity-plan and operate training and inference systems under real constraints.
- Mapped lessons
- 7
- Published now
- 0
- Full-arc estimate
- ≈19 hours
- Last edited
- 2026-08-11
Lesson sequence
Live units open into complete labs. Planned units stay visible to show the dependency path, but intentionally have no detail route.
- 01
The Accelerator Memory Hierarchy
PlannedReason from registers, SRAM, HBM, interconnect, and host memory to wall-clock performance.
Concept labAdvanced110 min estimate
- 02
Precision and Quantization as Error Budgets
PlannedCompare numeric formats and quantization methods through memory, throughput, calibration, and quality loss.
Failure labAdvanced120 min estimate
- 03
Continuous Batching and Queueing
PlannedModel prefill, decode, scheduling, tail latency, and throughput under mixed request shapes.
Systems labAdvanced120 min estimate
- 04
Parallelism for Inference
PlannedChoose tensor, pipeline, expert, and data parallelism from model shape and interconnect constraints.
Design reviewAdvanced120 min estimate
- 05
Distributed Training Without Topology Amnesia
PlannedMap optimizer state, gradients, activations, parameters, and collectives onto an actual cluster.
Systems labAdvanced135 min estimate
- 06
The Model-Serving Control Plane
PlannedDesign placement, rollout, autoscaling, health, model loading, and rollback independent of request execution.
Systems labAdvanced115 min estimate
- 07
Load-Test an AI Service
PlannedGenerate representative sequence shapes, concurrency, cancellations, and cache behavior while protecting quality signals.
Build labAdvanced110 min estimateArtifact: AI load-test plan