Arc 10 · Staff AI Engineer
Inference, Training, and AI Infrastructure
Connect model execution to hardware reality: memory movement, precision, batching, parallelism, schedulers, storage, and failure recovery.
Exit capability: Capacity-plan and operate training and inference systems under real constraints.
- Mapped lessons
- 7
- Published now
- 7
- Full-arc estimate
- ≈19 hours
- Last edited
- 2026-09-26
Lesson sequence
Live units open into complete labs. Planned units stay visible to show the dependency path, but intentionally have no detail route. A withdrawn unit is retained only at its previously advertised URL and is not presented as live.
- 01
The Accelerator Memory Hierarchy
LiveReason from registers, SRAM, HBM, interconnect, and host memory to wall-clock performance.
Concept labAdvanced110 min estimateArtifact: Accelerator memory traffic model
- 02
Precision and Quantization as Error Budgets
LiveCompare numeric formats and quantization methods through memory, throughput, calibration, and quality loss.
Failure labAdvanced120 min estimateArtifact: Quantization error-budget release gate
- 03
Continuous Batching and Queueing
LiveModel prefill, decode, scheduling, tail latency, and throughput under mixed request shapes.
Systems labAdvanced120 min estimateArtifact: Continuous batching capacity model
- 04
Parallelism for Inference
LiveChoose tensor, pipeline, expert, and data parallelism from model shape and interconnect constraints.
Design reviewAdvanced120 min estimateArtifact: Inference parallelism topology planner
- 05
Distributed Training Without Topology Amnesia
LiveMap optimizer state, gradients, activations, parameters, and collectives onto an actual cluster.
Systems labAdvanced135 min estimateArtifact: Distributed training topology audit
- 06
The Model-Serving Control Plane
LiveDesign placement, rollout, autoscaling, health, model loading, and rollback independent of request execution.
Systems labAdvanced115 min estimateArtifact: Model-serving control-plane rollout contract
- 07
Load-Test an AI Service
LiveGenerate representative sequence shapes, concurrency, cancellations, and cache behavior while protecting quality signals.
Build labAdvanced110 min estimateArtifact: AI load-test plan