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System Design

Latency Numbers Every Engineer Should Know

Order-of-magnitude latencies from L1 cache (~1 ns) to a cross-continent round trip (~150 ms). The point isn't the exact figure — it's the ratios: memory is ~100× faster than SSD, and a network hop dwarfs everything local.

Updated August 30, 2026 · 4 min read

The ladder (approximate, modern hardware)

Each step down is roughly an order of magnitude. Treat these as powers of ten, not exact numbers.

L1 cache reference	~1 ns
Branch mispredict	~3 ns
L2 cache reference	~4 ns
Mutex lock / unlock	~17 ns
Main memory (RAM) reference	~100 ns~100× an L1 hit
Compress 1 KB (Snappy/LZ4)	~2 µs
Read 1 MB sequentially from RAM	~3 µs
SSD random read (4 KB, NVMe)	~16 µs
Read 1 MB sequentially from SSD	~200 µsNVMe faster, SATA slower
Round trip in the same datacenter	~0.5 ms
Read 1 MB sequentially from HDD	~2–5 ms
HDD disk seek	~5–10 ms
Send 1 MB over 1 Gbps network	~8 ms
Round trip California ↔ Europe	~150 msspeed of light floor

The ratios that actually matter

RAM vs SSD (random)	~150× slower
RAM vs same-DC round trip	~5,000× slower
Same-DC vs cross-region round trip	~300× slower
One cross-region round trip	≈ 1.5 million L1 hitswhy chatty cross-region calls kill latency

In the interview

When you say “add a cache,” you’re claiming the hot path is memory-bound (~100 ns) not network-bound (~0.5–150 ms). Name which.
Tail latency is dominated by the slowest tier a request touches — usually disk or a cross-service hop, not CPU.
A design that makes N sequential cross-region calls has a latency floor of N × ~150 ms. Batch or co-locate.